ics673-01 mds 673-01 k 1 revision 110409 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com pll b uilding b lock description the ics673-01 is a low cost, high performance phase locked loop (pll) designed for clock synthesis and synchronization. included on the chip are the phase detector, charge pump, vo ltage controlle d oscillator (vco), and two output buffers. one output buffer is a divide by two of the other. through the use of external reference and vco dividers (the ics674-01), the user can customize the clock to lock to a wide variety of input frequencies. the ics673-01 also has an output enable function that puts both outputs into a high-impedance state. the chip also has a power down feature which turns off the entire device. for applications that r equire low jitter or jitter attenuation, see the mk2069. for a smaller package, see the ics663. features ? packaged in 16 pin soic ? access to vco input and feedback paths of pll ? vco operating range up to 120 mhz (5v) ? able to lock mhz range outputs to khz range inputs through the use of external dividers ? output enable tri-states outputs ? low skew output clocks ? power down turns off chip ? vco predivide to feedback divider of 1 or 4 ? 25 ma output drive ca pability at ttl levels ? advanced, low power, sub-micron cmos process ? single supply +3.3 v or +5 v 10% operating voltage ? industrial temperature range available ? forms a complete pll, using the ics674-01 ? for better jitter performance, please use the mk1575 note: eol for non-green parts to occur on 5/13/10 per pdn u-09-01 block diagram refin phase/ frequency detector vco 4 2 sel vcoin chcp up fbin down i cp i cp clk2 vdd mux 1 0 external feedback divider (such as the ics674-01) clock input cap pd (entire chip) vdd 2 3 gnd clk1 oe (both outputs) 2
pll b uilding b lock mds 673-01 k 2 revision 110409 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics673-01 pin assignment vco predivide select table 0 = connect pin directly to ground 1 = connect pin directly to vdd pin descriptions 12 1 11 2 10 fbin refin 3 9 vdd 4 vdd nc 5 gnd 6 clk1 7 gnd 8 gnd clk2 pd sel chgp oe vcoin cap 16 15 14 13 16 pin narrow (150 mil) soic sel vco predivide 04 11 pin number pin name pin type pin description 1 fbin input feedback clock i nput. connect the feedback clock to this pin. falling edge triggered. 2 vdd power connect to +3.3 v or +5 v and to vdd on pin 3. 3 vdd power connect to vdd on pin 2. 4 gnd power connect to ground. 5 gnd power connect to ground. 6 gnd power connect to ground. 7 chgp output charge pump output. connect to vcoin under normal operation. 8 vcoin input input to internal vco. 9 cap input loop filter return. 10 oe input output enable. active when high. tri-states both outputs when low. 11 sel input select pin for vco predivide to feedback divider per table above. 12 pd input power down. turns off entire chip when pin is low. outputs stop low. 13 clk2 output clock output 2. low skew divide by two version of clk1. 14 clk1 output clock output 1. 15 nc - no connect. nothing is conn ected internally to this pin. 16 refin input reference input. connect reference clock to this pin. falling edge is triggered.
pll b uilding b lock mds 673-01 k 3 revision 110409 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics673-01 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics673-01. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vdd=3.3v 5% or 5.0v 10%, ambient temperature -40 to +85 c, unless stated otherwise item rating supply voltage, vdd 7v all inputs and outputs -0.5v to vdd+0.5v ambient operating temperature 0 to +70 c industrial temperature -40 to +85 c storage temperature -65 to +150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature 0 +70 c power supply voltage (measured in respect to gnd) +3.13 +5.25 v parameter symbol conditions min. typ. max. units operating voltage vdd 3.13 5.50 v logic input high voltage v ih refin, fbin, sel 2v logic input low voltage v il refin, fbin, sel 0.8 v lf input voltage range v i 0vddv output high voltage v oh i oh = -25 ma 2.4 v output low voltage v ol i ol = 25ma 0.4 v output high voltage, cmos level v oh i oh = -8 ma vdd-0.4 operating supply current idd vdd = 5.0 v, no load, 40 mhz 15 ma short circuit current i os clk 100 ma input capacitance c i sel 5 pf
pll b uilding b lock mds 673-01 k 4 revision 110409 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics673-01 ac electrical characteristics vdd = 3.3v 5%, ambient temperature -40 to +85 c, c load at clk = 15 pf, unless stated otherwise vdd = 5.0v 10%, ambient temperature -40 to +85 c, c load at clk = 15 pf, unless stated otherwise note 1: minimum input frequency is limited by loop filter design. 1 khz is a practical minimum limit. external components the ics673-01 requires a minimum number of external components for proper operation. a decoupling capacitor of 0.01 f should be connected between vdd and gnd as close to the ics673-01 as possible. a series termination resistor of 33 ? may be used at the clock output. special considerations must be made in choosing loop components c s and c p . these can be found online at http://www.icst.com/products/telecom/loopfiltercap.htm avoiding pll lockup in some applications, the ics673-01 can ?lock up? at the maximum vco frequency. this is usually caused by power supply glitches or a very slow power supply ramp. this situation also occurs if the external divider starts to fail at high input frequencies. the usual failure mode of a divider circuit is that the output of the divider begins to miss clock edges. the phase detector interprets this as a too low output frequency and parameter symbol conditions min. typ. max. units output clock frequency (from pin clk) f clk sel = 1 1 100 mhz sel = 0 0.25 25 mhz input clock frequency (into pins refin or fbin) f ref note 1 8 mhz output rise time t or 0.8 to 2.0v 1.2 2 ns output fall time t of 2.0 to 0.8v 0.75 1.5 ns output clock duty cycle t dc at vdd/2 40 50 60 % jitter, absolute peak-to-peak t j 250 ps vco gain k o 190 mhz/v charge pump current i cp 2.5 a parameter symbol conditions min. typ. max. units output clock frequency (from pin clk) f clk sel = 1 1 120 mhz sel = 0 0.25 30 mhz input clock frequency (into pins refin or fbin) f ref note 1 8 mhz output rise time t or 0.8 to 2.0v 0.5 1 ns output fall time t of 2.0 to 0.8v 0.5 1 ns output clock duty cycle t dc at vdd/2 45 50 55 % jitter, absolute peak-to-peak t j 150 ps vco gain k o 190 mhz/v charge pump current i cp 2.4 a
pll b uilding b lock mds 673-01 k 5 revision 110409 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics673-01 increases the vco frequency. the feedback divider begins to miss even more clock edges and the vco frequency is continually increa sed until it is running at its maximum frequency. whether caused by power supply issues or by the external divider, the loop can only recover by powering down the circuit or asserting pd. the simplest way to avoid this problem is to use an external divider that always operates correctly regardless of the vco speed. figures 2 and 3 show that the vco is capable of high speeds. by using the internal divide-by-four and/or the clk2 output, the maximum vco frequency can be divided by 2, 4, or 8 and a slower counter can be used. using the ics673 internal dividers in this manner does reduce the number of frequencies that can be exactly synthesized by forcing the total vco divide to change in increments of 2, 4, or 8. if this lockup problem occurs, there are several solutions; three of which are described below. 1. if the system has a reset or power good signal, this should be applied to the pd pin, forcing the chip to stay powered down until the power supply voltage has stabilized 2. if no power good signal is available, a simple power-on reset circuit can be attached to the pd pin, as shown in figure 1. when the power supply ramps up, this circuit holds pd asserted (device powered down) until the capacitor charges. the circuit of figure 1a is adequate in most cases, but the discharge rate of capacitor c3 when vdd goes low is limited by r1. as this discharge rate determines the minimum reset time, the circuit of figure 1b may be used when a faster reset time is desired. the values of r1 and c3 should be selected to ensure that pd stays below 1.0 v until the power supply is stable. 3. a comparator circuit may be used to monitor the loop filter voltage as shown in fi gure 2. this circuit will dump the charge off the loop filter by asserting pd if the vco begins to run too fast and the pll can recover. a good choice for the comparator is the national semiconductor lmc7211bim5x. it is low power, version of the small (sot-23), low cost, and has high input impedance. the trigger voltage of the comparator is set by the voltage divider formed by r2 and r3. the voltage should be set to a value higher than the vco input is expected to run during normal operation. typically, this a. basic circuit r 1 c 3 pd ics673-01 vdd b. faster discharge r 1 c 3 pd ics673-01 vdd d 1 fig 1. power on reset circuits
pll b uilding b lock mds 673-01 k 6 revision 110409 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics673-01 might be 0.5 v below vdd. hysteresis should be added to the circuit by connecting r4. the clk output frequency may be up to 2x the maximum output clock frequency listed in the ac electrical characteristics above when the device is in an unlocked condition. make sure that the external divider can operate up to this frequency. explanation of operation the ics673-01 is a pll building block circuit that includes an integrated vco with a wide operating range. the device uses external pll loop filter components which through proper configuration allow for low input clock reference frequencies, such as a 15.7 khz hsync input. the phase/frequency detect or compares the falling edges of the clocks inputted to fbin and refin. it then generates an error signal to the charge pump, which produces a charge proportional to this error. the external loop filter integrates this charge, producing a voltage that then controls the frequency of the vco. this process continues until the edges of fbin are aligned with the edges of the refin clock, at which point the output frequency will be locked to the input frequency. figure 3. example configur ation -- generating a 20 mhz clock from a 200 khz reference. figure 2. using an external comparator to reset the vco chgp vcoin r z c 1 c 2 cap + - r 4 r 2 r 3 pd ics673-01 refin +3.3 or 5 v sel vdd 0.01 f fbin 200 khz 100 digital divider such as ics674-01 gnd clk2 cap 20 mhz vcoin c 1 r z c 2 200 khz oe pd 40 mhz clk1
pll b uilding b lock mds 673-01 k 7 revision 110409 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics673-01 determining the loop filter values the loop filter components consist of c s , c p , and r s . calculating these values is best illustrated by an example. using the example in figure 1, we can synthesize 20 mhz from a 200 khz input. the phase locked loop may be approximately described by the following equations: bandwidth damping factor, where: k o = vco gain (hz/v) i cp = charge pump current (a) n = total feedback divide from vco, including the internal vco post divider c s = loop filter capacitor (farads) r s = loop filter resistor (ohms) as a general rule, the bandwidth should be at least 20 times less than the reference frequency, i.e., in this example, using the above equation, bandwidth should be less than or equal to 10 khz. by setting the bandwith to 10khz and using the first equation, r s can be determined since all other variables are known. in the example of figure 1, n = 200, comprising the divide by 2 on the chip (vco post divider) and the external divide by 100. therefore, the bandwidth equation becomes: and r s = 26 k ? choosing a damping factor of 0.7 (a minimal damping factor than can be used to ensure fast lock time), damping factor equation becomes: and c s = 1.32 nf (1.2 nf is the nearest standard value). the capacitor c p is used to damp transients from the charge pump and should be approximately 1/20th the size of c s , i.e., therefore, c p = 60 pf (56 pf nearest standard value). to summarize, the loop filter components are: c s = 1.2 nf c p = 56 pf r s = 26 k ? when choosing either clk1 or clk2 to drive the feedback divider, idt recommends that clk2 be used so that the rising edges of clk1, clk2, and refin are all synchronized. if clk1 is used to feedback, clk2 may be either a rising or falling edge when compared to clk1 and refin. n bw r s k o i c p ?? 2 n ---------------- -------------- -- = r s 2 ------ k o i cp c s ?? n ---------------- ---------------- -- - = bw refin () 20 ? 0 ,000 r s 190 10 6 2.5 10 ? ?? ?? 2 200 ? --------------- ------------------ ----------------- ---------------- -- = 0 .7 25 000 , 2 ---------------- 190 10 6 2.5 10 6 ? c s ??? ? 200 ---------------------- ----------------- ------------------ --------------- -- = c p c s 2 0 ? ?
pll b uilding b lock mds 673-01 k 8 revision 110409 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics673-01 package outline and package dimensions (16 pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information *note: eol for non-green parts to occur on 5/13/10 per pdn u-09-01 while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature 673m-01i* ics673m-01 tubes 16 pin soic -40 to +85 c 673M-01IT* ics673m-01 tape and reel 16 pin soic -40 to +85 c index area 1 2 16 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 9.80 10.00 .3859 .3937 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
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